Test is an important step in the manufacture of semiconductor devices. The automatic test equipment (ATE) employed to carry out this task comprises sophisticated electronics capable of sending-test signals to, and capturing output signals from, one or more devices under test (DUTs). ATE channel hardware, typically referred to as “channels”, orchestrate this back and forth flow of signals.
Conventional channel circuitry, as shown in FIG. 1, feeds tester data signals (drive data) originating from a pattern generator 12 to a device-under-test (DUT) 14 via interface circuitry commonly referred to as pin electronics 16. Response signals from the DUT are captured and compared to expected data with the resulting comparison data fed to a failure processor 18 in order to determine pass or fail conditions. The “expected” and “drive” data are typically programmed in the pattern generator vector memory (not shown) to occur at precise timings, in accordance with how the DUT should behave. If the data captured from the DUT fails to correspond with an expected condition, the device is considered to have failed that aspect of the test.
Modem semiconductor devices are trending towards employing multiple processing cores on the same piece of silicon, or chip. Adding to this complexity is the overall trend towards implementing asynchronous on-chip communication protocols. The end result is an exponential increase in the chip gate count, yet only modest increases in the available pin counts. Consequently, multiple sub-circuits often share the pins (interface).
This shared interface scheme is illustrated generally in FIG. 2, where a plurality of device-under-test subcircuits 20a–20c send data packets to a DUT communications port 22. The communications port serves as the gatekeeper to accessing the DUT output pin 24. Each of the subcircuits may be clocked by a separate clock having a frequency different from not only the other subcircuits, but also possibly different from the communications port clock. An asynchronous arbitrator 26 handles the sequencing of the data packets to the DUT output pin.
During typical DUT operation, as shown in FIGS. 3A and 3B, the shared interface scheme may cause problems (for conventional ATE) known as “cycle slipping”, and “out-of-order data”. Cycle slipping often results from the communications port clock operating at a frequency different than that of the subcircuit clocks. The result may be that the DUT output pin sees periods of “idle” data, or a number of cycles of non-packetized information. These idle periods may occur at the beginning of a data transmission, or between packets of data.
Out-of-order data often results from the subcircuits attempting to access the communications port 22 (FIG. 2) on the same clock edge, or having differing delays due to environmental conditions. FIG. 3B illustrates the general concept on how an expected sequencing may be disturbed into an out-of-order packet sequence.
Both “cycle slipping” and “out of order” data present unique challenges to automatic test equipment. As previously described in the context of FIG. 1, traditional ATE relies on the comparison of expected data, at expected timings, to actual data and actual timings. Providing unknown and unexpected delay and data sequences in the actual DUT data for conventional ATE often results in post-test data descrambling to determine whether the device failed or passed. This may involve substantial modifications to the test program and create substantial overhead in program development and test time.
What is desired and currently unavailable is a test solution for non-deterministic data that provides substantially real-time validation results and maximizes flexibility for the device manufacturer while reducing test costs. The apparatus and method of the present invention provides such a solution.